1. Field of the Invention
The present invention relates to active semiconductor backplanes suitable for use with a spaced opposed substrate, commonly a counterelectrode, to form a cell, and to devices comprising such backplanes.
2. Discussion of Prior Art
The device which is particularly described in this specification in connection with a preferred embodiment is a spatial light modulator in the form of a smectic liquid crystal layer disposed between an active semiconductor backplane and a common front electrode. It was developed in response to a requirement for a fast and, if possible, inexpensive, spatial light modulator comprising a relatively large number of pixels with potential application not only as a display device, but also for other forms of optical processing such as correlation and holographic switching. Our copending International Patent Applications even filing and priority dates (PCT/GB99/04285, U.S. Ser. No. 09/868,219, priority GB9827952.4; PCT/GB99/04286 and PCT/GB99/04276, U.S. Ser. No. 09/868,239 and U.S. Ser. No. 09/868,220, both priority GB9827965.6; PCT/GB99/04282, U.S. Ser. No. 09/446,325, priority GB9827900.3; PCT/GB99/04274, U.S. Ser. No. 09/868,218, priority GB9827964.9; PCT/GB99/04275, U.S. Ser. No. 09/868,217, priority GB9827945.8; and PCT/GB99/04260 and PCT/GB99/04277, U.S. Ser. No. 09/868,241 and U.S. Ser. No. 09/868,242, both priority GB 9827944.1) relate to other inventive aspects associated with the spatial light modulator.
During the course of development of the spatial modulator, a series of problems were encountered and dealt with, and the solutions to these problems (whether in the form of construction, function or method) are not necessarily restricted in application to the embodiment, but will find other uses. Thus not all of the aspects of the present invention are limited to liquid crystal devices, nor to spatial light modulators.
Nevertheless, it is useful to commence with a discussion of the problems encountered in developing the embodiment to be described later.
The liquid crystal phase has been recognised since the last century, and there were a few early attempts to utilise liquid crystal materials in light modulators, none of which gave rise to any significant successful commercial use. However, towards the end of the 1960""s and in the 1970""s, there was a renewed interest in the use of liquid crystal materials in light modulating, with increasing success as more materials, and purer materials became available, and as technology in general progressed.
Generally speaking, this latter period commenced with the use of nematic and cholesteric liquid crystal materials. Cholesteric liquid crystal materials found use as sensors, principally for measuring temperature or indicating a temperature change, but also for responding to, for example, the presence of impurities. In such cases, the pitch of the cholesteric helix is sensitive to the parameter to be sensed and correspondingly alters the wavelength at which there is selective reflection of one hand of circularly polarised light by the helix.
Attempts were also made to use cholesteric materials in electro-optic modulators, but during this period the main thrust of research in this area involved nematic materials. Initial devices used such effects as the nematic dynamic scattering effect, and increasingly sophisticated devices employing such properties as surface induced alignment, the effect on polarised light, and the co-orientation of elongate dye molecules or other elongate molecules/particles, came into being.
Some such devices used cells in which the nematic phase adopted a twisted structure, either by suitably arranging surface alignments or by incorporating optically active materials in the liquid crystal phase. There is a sense in which such materials resemble cholesteric materials, which are often regarded as a special form of the nematic phase.
Initially, liquid crystal light modulators were in the form of a single cell comprising a layer of liquid crystal material sandwiched between opposed electrode bearing plates, at least one of the plates being transparent. The thickness of the liquid crystal layer in nematic cells is commonly around 20 to 100 microns, and there is a correspondingly small unit capacitance associated with a nematic liquid crystal cell. Furthermore, the switching time from a wholly xe2x80x9cOFFxe2x80x9d state to a wholly xe2x80x9cONxe2x80x9d state tends to be rather long, commonly around a millisecond. Relaxation back to the xe2x80x9cOFFxe2x80x9d state can be somewhat longer, unless positively driven, but the xe2x80x9cOFFxe2x80x9d state is the only stable one.
At the same time, electro-optic nematic devices comprising a plurality of pixels were being devised. Initially, these had the form of a common electrode on one side of a cell and a plurality of individually addressable passive electrodes on the other side of the cell (e.g. as in a seven-segment display), or, for higher numbers of pixels, intersecting passive electrode arrays on either side of the cell, for example row and column electrodes which were scanned. While the latter arrangements provided considerable versatility, there were problems associated with cross-talk between pixels.
The situation was exacerbated when analogue (grey scale) displays were required by analogue modulation of the applied voltage, since the optical response is non-linearly related to applied voltage. Addressing schemes became relatively complicated, particularly if dc balance was also required. Such considerations, in association with the relative slowness of switching of nematic cells, have made is difficult to provide real-time video images having a reasonable resolution.
Subsequently, active back-plane devices were produced. These comprise a back plane comprising a plurality of active elements, such as transistors, for energising corresponding pixels. Two common forms are thin film transistor on silica/glass backplanes, and semiconductor backplanes. The active elements can be arranged to exercise some form of memory function, in which case addressing of the active element can be accelerated compared to the time needed to address and switch the pixel, easing the problem of displaying at video frame rates.
Active backplanes are commonly provided in an arrangement very similar to a dynamic random access memory (DRAM) or a static random access memory (SRAM). At each one of a distributed array of addressable locations, a SRAM type active backplane comprises a memory cell including at least two coupled transistors arranged to have two stable states, so that the cell (and therefore the associated liquid crystal pixel) remains in the last switched state until a later addressing step alters its state. Each location electrically drives its associated liquid crystal pixel, and is bistable per se, i.e. without the pixel capacitance. Power to drive the pixel to maintain the existing switched state is obtained from busbars which also supply the array of SRAM locations. Addressing is normally performed from peripheral logic via orthogonal sets (for example column and row) addressing lines.
In a DRAM type active backplane, a single active element (transistor) is provided at each location, and forms, together with the capacitance of the associated liquid crystal pixel, a charge storage cell. Thus in this case, and unlike a SRAM backplane, the liquid crystal pixels are an integral part of the DRAM of the backplane. There is no bistability associated with the location unless the liquid crystal pixel itself is bistable, and this is not normally the case so far as nematic pixels are concerned. Instead, reliance is placed on the active element providing a high impedance when it is not being addressed to prevent leakage of charge from the capacitance, and on periodic refreshing of the DRAM location.
Thin film transistor (TFT) backplanes comprise an array of thin film transistors distributed on a substrate (commonly transparent) over what can be a considerable area, with peripheral logic circuits for addressing the transistors, thereby facilitating the provision of large area pixellated devices which can be directly viewed. Nevertheless, there are problems associated with the yields of the backplanes during manufacture, and the length of the addressing conductors has a slowing effect on the scanning. When provided on a transparent substrate, such as of glass, TFT arrays can actually be located on the front or rear surface of a liquid crystal display device.
In view of their overall size, the area of the TFT array occupied by the transistors, associated conductors and other electrical elements, e.g. capacitors is relatively insignificant. There is therefore no significant disadvantage in employing the SRAM configuration as opposed to the DRAM configuration. This sort of backplane thus overcomes many of the problems associated with slow switching times of liquid crystal pixels.
Generally, the active elements in TFT backplanes are diffusion transistors and the like as opposed to FETS, so that the associated impedances are relatively low and associated charge leakage relatively high in the xe2x80x9cOFFxe2x80x9d state.
Semiconductor active backplanes are limited in size to the size of semiconductor substrate available, and are not suited for direct viewing with no intervening optics. Nevertheless their very smallness aids speed of addressing of the active elements. This type of backplane commonly comprises FETs, for example MOSFETs or CMOS circuitry, with associated relatively high impedances and relatively low associated charge leakage in the xe2x80x9cOFFxe2x80x9d state.
However, the smallness also means that the area of the overall light modulation (array) area occupied by the transistors, associated conductors and other electrical elements, e.g. capacitors can be relatively significant, particularly in the SRAM type which requires many more elements than the DRAM type. Being opaque to visible light, a semiconductor backplane would provide the rear substrate of a light modulator or display device.
In contrast to the type of RAM associated with computing, the pixel circuits, and more significantly the pixel transistors, are often at least partially exposed to light. This can lead to problems, especially with DRAM type backplanes where the pixels are part of the DRAM circuit, including photo-induced conductivity and charge leakage.
Smectic Liquid Crystal Electro-Optic Cells
At a later period still, substantial development occurred in the use of smectic liquid crystals. These have potential advantages over nematic phases insofar as their switching speed is markedly greater, and with appropriate surface stabilisation the ferroelectric smectic C phases should provide devices having two stable alignment states, i.e. a memory function.
The thickness of the layer of liquid crystal material in such devices is commonly much smaller than in the corresponding nematic devices, normally being of the order of a few microns at most. In addition to altering the potential switching speed, this increases the unit capacitance of a pixel, easing the function of a DRAM active backplane in retaining a switched state at a pixel until the next address occurs.
However, as the thickness of the liquid crystal approaches the thicknesses associated with the underlying structure of the backplane and with any possible deformation of the liquid crystal cell structure by flexing or other movement of the substrates, problems arise, for example as to the uniformity of response across the pixel area, and the capability for short circuiting across the cell thickness.
In the smectic liquid crystal phase, the molecules exhibit positional order (xe2x80x9clayersxe2x80x9d) in addition to the orientational order exhibited by the cholesteric and nematic phases. There are a number of different smectic sub-phases which differ in the orientational order within the overall structure of the smectic layers, the most common being the smectic A phase (SmA) and the smectic C phase (SmC).
The common alignment for smectic materials is planar (molecules generally parallel to the major cell surfaces) with the smectic layers normal to the plane of the cell, as this permits the field to be applied across the cell thickness. It is possible to obtain homeotropic alignment with the smectic layers in the cell plane, and such a device could provide a fast refractive index modulator. However, in order to apply appropriate electric fields for switching, very small electrode gaps are required and therefore such devices tend to have very small active areas, and as a consequence this type of device is relatively uncommon.
In the smectic A phase the director is normal to the plane of the layers. Application of an electric field perpendicular to the director causes the latter to tilt about an axis parallel to the applied field by an amount approximately linearly dependent of field strength, making it possible to achieve analogue grey scale modulation. Polarisation of the light is affected, so that intensity or phase modulation may be achieved, and since the rotation of the director is in the plane of the cell, normally incident light is always perpendicular to the optic axis of the material. Coupled with the thinness of the cell, this leads to improved viewing angles for such devices. This effect, called the electroclinic effect, is extremely fast, switching times down to around 100 nanoseconds having been observed.
In the smectic C phase, the director forms a constant (xe2x80x9ctiltxe2x80x9d) angle with the plane of the smectic layers. The tilt angle depends on the material and the temperature, and defines a cone with its tip on the smectic layer and its axis normal to the layer, all possible positions of the director lying on the cone surface. In the bulk of a chiral smectic C phase (SmC*) the director precesses from layer to layer as in a helix.
In the chiral smectic C phase, liquid crystal materials are ferro-electric, having a permanent dipole, sometimes termed spontaneous polarisation (Ps). In the bulk material, Ps rotates in the plane of the layer as the director precesses, so no net effect is observable. Bulk ferro-electricity can be observed if the precession is suppressed, either by surface stabilisation of the director positions such that only the two orientations of director which lie in the plane of the device are possible, and/or by back-doping with a chiral material of the opposite hand.
Smectic C* materials can be broadly divided into two classes known as high and low tilt materials respectively. Class I materials have the phase sequence isotropicxe2x80x94nematicxe2x80x94smectic A*xe2x80x94smectic C*, and tend be low tilt materials, having tilt angles generally grouped up to around 22.5xc2x0 (cone angle of 45xc2x0); class II materials have the phase sequence isotropicxe2x80x94nematicxe2x80x94smectic C*, and tend to be high tilt materials with greater tilt angles. Materials with a cone angle greater than 75xc2x0 are rare, although for holographic applications, which require phase modulation, a cone angle of 90xc2x0 would be ideal.
With low tilt materials, the smectic layers are inclined relative to the cell surface rather than at right angles, such that the director cone has a tilted axis and its surface is tangential to the cell surface. For high tilt materials the cone axis is normal to the cell surface.
When the structure is surface stabilised, then in theory, at least for Class I materials there is no preference between the two states of a low tilt material and a bistable structure should result. Surface stabilisation can be achieved simply by making the layer in the cell thin. The two states will have different effects on polarised light, and so can provide intensity or phase modulation. In practice, it is very difficult or impossible to obtain true bistability, especially on silicon backplanes and there will a slight preference for one state over the other. Nevertheless, this should give rise to relatively long relaxation times.
For high tilt materials, the two states are not equal, and one state is preferred over the other, so that there is monostability in the absence of any other factor. The two states are such that phase modulation of light may be obtained, and, indirectly, intensity modulation, e.g. in holographic applications. Both high and low tilt materials may be used in the spatial light modulator of the invention.
Stability/Relaxation
The presence of the spontaneous polarisation, and its realignment as the liquid crystal molecules realign under the influence of an electric field, leads to a significant additional current or charge flow during realignment, e.g. between electrodes either side of a smectic layer. A pixel of area A will consume a charge of 2AP, during switching. This factor is particularly important when pixel switching is controlled by DRAM type of active backplane, when pixel capacitance and Ps become important design parameters. It should also be noted that charge consumption reduces the field across the electrodes in such devices if the addressing pulse is insufficiently long to accommodate pixel switching, as in the present preferred embodiment.
As has already been noted, the use of the backplanes described herein is not limited to liquid crystal devices. However, these backplanes are particularly suited for use in the manufacture of liquid crystal devices. Again, although it is possible to employ nematic or cholesteric materials in such devices, it is preferred to employ smectic materials because of their faster switching action. Also, in the case of using a DRAM type active backplane (this does not apply when the backplane is the SRAM type since power/current can be continuously applied to each pixel), the ability to extend the relaxation time, or even to obtain a bistable effect, once the pixel has been placed in the desired state.
One advantage of having a fast switching time in the case where relaxation occurs lies in the increase of the fraction of the pixel repeat address period usable for viewing time. Another advantage, particularly where optical processing is concerned is the increase in data throughput.
Pixel Structurexe2x80x94Switching and Address Times
When using a SRAM type backplane to switch a capacitive element the time necessary to address the location on the backplane can be as small as is necessary to switch that location, regardless of whether the capacitive element has responded. The location is always coupled to the power supply, and can continue to supply power (current/voltage) to the capacitive element after the addressing pulse has ceased.
By contrast, power is supplied to a capacitive element from a DRAM location only while addressing is taking place, after which the active element (transistor) is turned off. If the addressing pulse is insufficiently long for transfer of the requisite amount of charge, the capacitive element is incompletely switched. This is likely to occur, for example, when the capacitive element includes ferroelectric material, as in some smectic liquid crystal cells, and the addressing time is short, for example in a large scale array.
One solution is to provide an additional xe2x80x9cslugxe2x80x9d capacitance which is rapidly charged during the addressing pulse and so can provide a reservoir of charge while the capacitive element switches over a longer time period.
In a first aspect the invention provides a semiconductor active backplane including an array of addressable active elements on a semiconductor substrate for selectively energising respective first electrodes of the array, wherein at least part of the region beneath a said first electrode is formed as a depletion region whereby in use it acts as a reverse biassed capacitative diode characterised in that at least one charge trapping implant is provided adjacent but spaced from said depletion region.
In a second closely related aspect the invention provides a semiconductor active backplane including an array of addressable active elements on a semiconductor substrate for selectively energising respective first electrodes of the array, wherein at least part of the region beneath a said first electrode is formed as a depletion region whereby in use it acts as a reverse biassed capacitative diode characterised in that a guard ring is provided over or around the periphery of said depletion region to prevent or hinder charge carriers from crossing between the depletion region and the rest of the substrate.
In a third aspect the invention provides a semiconductor active backplane including an array of addressable active elements on a semiconductor substrate for selectively energising respective first electrodes of the array, characterised in that at least part of the region beneath a said first electrode is provided by individual capacitor plates formed beneath the electrode, one coupled to the substrate and the outer coupled to the electrode.
The first second and third aspects of the invention are particularly useful where the active element comprises a single transistor as in a DRAM type backplane.
In U.S. Pat. No. 4,839,707 (Shields) part of a dielectric layer is employed as a capacitive region between a source region and a silicon substrate. The dielectric layer is insulating, and the construction does not involve two distinguishable capacitor plates below the addressable electrode, one coupled to the addressable electrode, the other coupled to the substrate, as in embodiments of the present invention.
In U.S. Pat. No. 5,537,234 (Williams et al) trench capacitors are formed in the rear surface of a semiconductor layer, which layer is adhered to a substrate and provides transistors in an array. The capacitors lie below addressable electrodes but they neither comprise depletion regions, nor act as reverse biassed diodes. Furthermore, the construction involves only one plate, as opposed to two individual electrodes, one coupled to an addressable electrode and one coupled to the substrate.
Electrostatic Stabilisation
Once the capacitive element has been switched, it is still necessary to maintain the element in its switched state, at least until it is energised again. Again SRAM type backplanes do this successfully by virtue of their continuous coupling to the power supply lines.
For DRAM type backplanes, it is necessary to note that the charge consumption which occurs when a pixel is switched in one direction gives rise to a corresponding generation of charge when the pixel switches in the other direction. Therefore, if a switched pixel is completely electrically isolated, charge cannot flow and the pixel cannot relax. In operation of a DRAM type array, this may be effected by turning off all the transistors of the array, and in the preferred embodiment this is made possible by applying a global reset signal NRAR to the row scanners.
In practice, charge leakage cannot be completely eliminated, and so relaxation will occur, but over an extended period. A common cause of charge leakage is photoconductivity associated with the slug capacitance mentioned earlier and/or photoconductive or other leakage currents in the associated switching transistor of the DRAM array. This is particularly marked with DRAM type backplanes for optical use, where incident illumination can penetrate directly or indirectly to the underlying backplane structure, thereby causing photoconduction.
Electrical isolation is thus a useful but imperfect tool for prolonging relaxation times. It will be appreciated that whether a long relaxation time is achieved through an appropriate choice of material and cell design, or by electrical isolation, the important factor is that sufficient time can be allowed between successive addressings of any pixel for it to be maintained essentially in its desired state. Particularly in the case of DRAM type backplanes it is important that the design is such that charge leakage is minimised.
Thus in a fourth aspect the invention provides a semiconductor active backplane including an array of addressable active elements on a semiconductor substrate for energising respective first electrodes, and first and second orthogonal sets of addressing conductors, a respective pair of addressing conductors, one from each set, being associated with the addressing of a corresponding active element, characterised in that substantially the whole of each active element is covered by a said addressing conductor in the form of a metallic conductor. In a fifth closely related aspect, substantially the whole of each element is covered by a said pair of addressing conductors in the form of metallic conductors. In one embodiment of the fifth aspect the active element is sited below the crossover between row and column conductors.
In all the above aspects of the invention where each said active element is connected to a metal electrode on said insulating layer, the array of said metal electrodes thus formed preferably covers more than 65%, and more preferably more than 80%, of the area of said array.
It may be possible to regard the type of construction of the certain aspects of the invention as being disclosed with respect to thin film transistor (TFT) array active backplanes; of which the following are exemplary disclosuresxe2x80x94EP 0762184 (Sharp KK); EP 0708356 (Sony); EP 0603866 (Sony); EP 0542579 (Sharp KK); U.S. Pat. No. 5,777,703 (Nishikawa); U.S. Pat. No. 5,691,782 (Nishikawa); U.S. Pat. No. 5,414,283 (den Boer).
Similarly EP 0877283 (Sanyo); EP 0793135 (Citizen Watch); EP 0752611 (OIS Optical Imaging Systems, Inc); and EP 0685757 (Matsushita) might be considered exemplary disclosures of thin film arrays in which an electrode is covered by an insulating film through which a connection is made to a larger reflective conductor over the insulating film.
Nevertheless, there are very real differences between TFT arrays and active semiconductor backplanes, not the least of which is that TFT arrays are much larger and transparent. It is believed that the effects of incident light on the transistors or other active elements in active semiconductor backplanes from has not heretofore been considered or even recognised, and that as a result no positive steps have been taken to protect such elements in the manners now proposed.